1. Field of the Invention
The invention relates to computing systems and, more particularly, to managing multiple I/O transactions in a multicore multiprocessing system.
2. Description of the Related Art
In recent years, efforts have been made to further increase the performance of microprocessors by incorporating more and more functionality onto a single chip. While such an approach may provide performance enhancements, a number of complications may arise. For example, when multiple independent I/O devices of different bus architectures, with no knowledge of caches, are embedded within a single processor with multiple independent memory caches, certain problems concerning coherency must be addressed. Ideally, each I/O device should see a consistent unified view of memory, each cache should treat all I/O transactions as if they came from the same I/O device, all caches should remain coherent, and messages to various threads should not get out of order.
Accordingly, an effective method and mechanism for managing I/O transactions in a chip multiprocessor is desired.